`timescale 1ns / 1ps

module inst_mem(clka, addra, douta);
  input clka;
  input [15:0] addra;
  output reg[15:0] douta;

  always @(addra)
    begin
      case(addra)
        0: douta <= 16'h3042; // LDC R0, 0x42
        1: douta <= 16'h3103; // LDC R1, 0x03
        2: douta <= 16'h2F01; // ADD R15, R0, R1
        3: douta <= 16'h2EF1; // ADD R14, R15, R1
        4: douta <= 16'h1E00; // ST R14, 0
        5: douta <= 16'h0E00; // LD R14, 0
        6: douta <= 16'h2DE1; // ADD R13, R14, R1 : R13 = 0x4b
        7: douta <= 16'hB000; // END
        default: douta <= 16'h0000;
      endcase
    end

endmodule