`timescale 1ns / 1ps

module inst_mem(clka, addra, douta);
  input clka;
  input [15:0] addra;
  output reg[15:0] douta;

  always @(addra)
    begin
      case(addra)
        0: douta <= 16'h300A; // LDC R0, #10
        1: douta <= 16'h3103; // LDC R1, #3
        2: douta <= 16'h3202; // LDC R2, #2
        3: douta <= 16'h9301; // DIV R3, R0, R1 -> R3 = 3
        4: douta <= 16'h9402; // DIV R4, R0, R2 -> R4 = 5
        5: douta <= 16'hA501; // MOD R5, R0, R1 -> R5 = 1
        6: douta <= 16'hB000; // END
        default: douta <= 16'h0000;
      endcase
    end

endmodule