`timescale 1ns / 1ps

module inst_mem(clka, addra, douta);
  input clka;
  input [15:0] addra;
  output reg[15:0] douta;

  always @(addra)
    begin
      case(addra)
        0: douta <= 16'h3064;
        1: douta <= 16'h3101;
        2: douta <= 16'h3202;
        3: douta <= 16'h3301;
        4: douta <= 16'hE320;
        5: douta <= 16'h2221;
        6: douta <= 16'h4402;
        7: douta <= 16'h6402;
        8: douta <= 16'h70FC;
        9: douta <= 16'h3202;
        10: douta <= 16'h4702;
        11: douta <= 16'h670B;
        12: douta <= 16'h3402;
        13: douta <= 16'h3600;
        14: douta <= 16'h8542;
        15: douta <= 16'h4705;
        16: douta <= 16'h6704;
        17: douta <= 16'hE650;
        18: douta <= 16'h2441;
        19: douta <= 16'h70FB;
        20: douta <= 16'h2221;
        21: douta <= 16'h70F5;
        22: douta <= 16'h3202;
        23: douta <= 16'h4702;
        24: douta <= 16'h6706;
        25: douta <= 16'hD420;
        26: douta <= 16'h2221;
        27: douta <= 16'h54FC;
        28: douta <= 16'h4F21;
        29: douta <= 16'h70FA;
        30: douta <= 16'hB000;
        default: douta <= 16'h0000;
      endcase
    end

endmodule